Semiconductor charge transfer devices (CTD) involve electrically controlled sequential shift-register operations on localized charge packets (accumulations) in a semiconductor medium.
Charge transfer devices in the semiconductor art fall into two main categories, the so-called "charge coupled device" (CCD) and integrated circuit versions of the "bucket brigade device" (BBD). In either version, a spatially periodic electrode metallization pattern on a major surface of a semiconductor body coated with oxide defines a sequence of integrated MOS (metal-oxide-semiconductor) type capacitors, so that localized electrical charge "packets" (accumulations) in the semiconductor can be shifted through the semiconductor sequentially between adjacent MOS capacitors by sequential (clock) electrical voltage pulses applied to the electrodes. These charge packets are initially injected at the input end of a chain of such MOS capacitors, in accordance with a stream of digital or analog information. For example, in the binary digital case, the stream of information is in the form of injected charges versus no injected charges at appropriate moments of the clock voltage pulse sequence. In general, there are as many MOS-type capacitors (storage sites) per "storage cell" as there are phases in just one full cycle of the voltage pulse sequences which drive the CTD. Thus, in any event, a semiconductor charge transfer device is a form of shift-register device.
In the CCD version of a CTD, the charge packets in the semiconductor, when not being shifted, are localized as isolated inversion layers at the oxide-semiconductor interface. These localized charge packets are sequentially shifted through the semiconductor under the influence of the clock. In the BBD version, the injected charges (when not being shifted) are localized as excess majority charge carriers in the diffused (or implanted) regions of localized P-N junctions previously fabricated at the oxide-semiconductor interface; and this excess charge (not necessarily the same charge carriers originally injected) is shifted through the semiconductor under the influence of the clock.
It should be understood of course that ordinarily in present day semiconductor charge transfer devices, the semiconductor medium is silicon and the oxide is silicon dioxide; however, other suitable semiconductor-insulator combinations may be used in general. Thus, the term "oxide" in connection with CTDs can refer to any such suitable insulator.
An important type of CTD involves the serial-parallel-serial transfer path configuration. Such a configuration comprises an initial horizontal row line of say M cells, a rectangular matrix of M columns and say N rows of cells, and a final horizontal row line of M cells, where both M and N are assumed to be integers for the sake of ease of explanation only. In operation, a sequential stream of say M packets is first sequentially shifted longitudinally through a first horizontal row line of M successive transfer cells until each of the M cells is filled with a different one of the M packets of the stream. Then, all of these M packets are simultaneously shifted transversely through a different vertical column line. Each column has N successive cells, thereby forming the MxN matrix of cells, M columns and N rows (plus the initial and the final row lines). After the packets have been thus shifted through the N column cells, each of the packets is fed into a different cell of the final horizontal row line of M cells. Then, the packets in this final horizontal row line are sequentially shifted longitudinally (through this final row line itself) to an output detector. Each and every packet is thus delayed by the serial-parallel-serial array by an amount corresponding to shifting through the same total number of cells, that is, (M+N+1) cells. However, each column of the cell can suffer from a different total amount of "dark current" source strengths and thereby impose a different "dark current background" on each of the M packets while being transferred through a different one of the M columns.
Moreover, even if the dark current were the same throughout all the cells in the M columns, different packets would still suffer different backgrounds due to the dark current background sources along the initial and along the final horizontal row lines. This difference in backgrounds occurs even if these dark current sources also all have the same strength in each cell, owing to the lack of symmetry of dark current effect on the packets in the final row line with respect to the initial row line. This lack of symmetry arises because some of the dark current charge buildup generated in the initial row line is being constantly removed by ("dumped into") the substrate at the end of this initial row line located on the opposite end thereof from the input end, whereas all of the charge due to dark current generated in the final row line ultimately appears at the detector at the output end of the final row line. Thus, even in the case of an array with each cell having the same dark current (uniformly spatially distributed sources of dark current background), a ramp of dark current background is built up in the initial row line, whereas the dark current background contribution of the cells in the final row line is the same for all packets. Therefore, the charge packets which are shifted through more cells of the initial row line (and hence correspondingly fewer cells in the final row line) suffer from more background charge on arrival at the detector than the charge packets which are shifted through more cells of the final row line (and correspondingly fewer cells of the initial row line).
In the case of linear transfer path configurations in a semiconductor CTD, where each and every charge packet passes through the same transfer path, the amount of dark current charge added to the packets will vary with the temperature of device. Accordingly, unavoidable device temperature variations tend to jeopardize the stability even in the case of linear path transfer devices.
It would therefore be desirable to have means for reducing the background due to dark current sources in semiconductor charge transfer devices, whether of the serial-parallel-serial or linear transfer path configuration.